AMD has formally confirmed that its upcoming EPYC “Venice” processor line will probably be amongst the primary merchandise manufactured utilizing TSMC’s superior 2nm (N2) course of node. This announcement celebrates the long-standing partnership between AMD and TSMC and signifies a significant step ahead in high-performance computing (HPC) know-how. The Venice collection, based mostly on AMD’s future Zen 6 and Zen 6c architectures, is predicted to launch in 2026 and can mark a generational leap in CPU design and manufacturing.
In response to AMD, the EPYC Venice processors have reached the “tape-out” stage, that means their designs have been finalized and are actually prepared to start manufacturing. This milestone positions Venice because the trade’s first HPC-oriented chip to achieve tape-out utilizing the N2 course of. The upcoming EPYC 9006 household will comply with the present EPYC 9005 “Turin” technology and can possible debut within the latter half of 2026, following AMD’s typical launch cadence.
✅ Our next-gen EPYC processor, codenamed “Venice,” is the primary HPC product within the trade to be taped out and introduced up on the TSMC superior #2nm (N2) course of know-how.
— AMD (@AMD) April 14, 2025
Though AMD has not disclosed detailed specs of the Zen 6 structure, expectations are excessive for important efficiency positive aspects over Zen 5. Enhancements could embrace elevated core counts and architectural refinements aimed toward additional optimizing effectivity and computational energy. These developments will cater to demanding HPC workloads equivalent to scientific analysis, simulations, and large-scale information processing.
TSMC’s N2 course of introduces a number of key improvements, most notably the transition to GAAFET (Gate-All-Round Area-Impact Transistor) know-how. GAAFETs provide improved management over electrical present, resulting in better energy effectivity and better transistor density. Moreover, the know-how permits chip designers to fine-tune transistor dimensions for efficiency, energy, or balanced optimization, providing enhanced flexibility in chip engineering.
Manufactured within the US
#TogetherWeAdvance: Our deep partnership with TSMC is bringing modern applied sciences to market that may energy probably the most demanding information heart purposes of the long run. https://t.co/vFLf3v7JuS pic.twitter.com/a1ilYdKf7S
— AMD (@AMD) April 14, 2025
In one other strategic transfer, AMD has confirmed that its present EPYC 9005 collection has been validated for manufacturing at TSMC’s Fab 21 facility in Arizona, USA. This manufacturing facility is TSMC’s first within the U.S. and a part of a broader initiative to diversify world semiconductor manufacturing. Fab 21 focuses on 5nm and 4nm processes, and whereas no actual timeline was shared, manufacturing of the EPYC 9005 chips in Arizona is predicted to start later in 2025, with additional bulletins anticipated.
